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Process Development Team Memory Division Samsung Electronics Co. Ltd. | 論文
- A Process Integration of (Ba, Sr) TiO_3 Capacitor into 256M DRAM
- Formation of High-Temperature Stable Co-Silicide from Co_Ta_/Si Systems
- The Formation of High Temperature Stable Co-Silicide from Co_Ta_x/Si Systems
- Low Dielectric Constant 3MS α-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process
- Evaluation of PECVD a-SiC:H as a Cu Diffusion Barrier Layer of Cu Dual Damascene Process
- A 0.24μm PRAM Cell Technology Using N-Doped GeSbTe Films(Phase Change RAM)(New Era of Nonvolatile Memories)
- Innovative Al Damascene Process for Nanoscale Interconnects
- Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
- Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
- Optimum TiSi_2 Ohmic Contact Process for Sub-100nm Devices
- A Study on the Germano-Silicide Formation in the Ni/Si_Ge_x System for CMOS Device Applications
- Preparation and Electrical Properties of SrTiO3 Thin Films Deposited by Liquid Source Metal-Organic Chemical Vapor Deposition (MOCVD)
- Rugged Metal Electrode (RME) for High Density Memory Devices : Surfaces, Interfaces, and Films
- Structural and Electrical Properties of Ba_Sr_TiO_3 Films on Ir and IrO_2 Electrodes
- Preparation and Characterization of Iridium Oxide Thin Films Grown by DC Reactive Sputtering
- Effects of Step Coverage, Cl Content and Deposition Temperature in TiN Top Electrode on the Reliability of Ta_2O_5 and Al_2O_3 MIS Capacitor for 0.13μm Technology and Beyond
- Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65nm Technology Nodes
- Ni Germano-Salicide Technology for High Performance MOSFETs
- Ni Germano-Salicide Technology for High Performance MOSFETs
- FEOL Process for Sub-100nm DRAM