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Process Development Team Memory Division Samsung Electronics Co. Ltd. | 論文
- FEOL Process for Sub-100nm DRAM
- Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques
- Control of Microscratches in Chemical-Mechanical Polishing Process for Shallow Trench Isolation
- Double-Patterning Technique Using Plasma Treatment of Photoresist
- Hot-Spot Detection and Correction Using Full-Chip-Based Process Window Analysis
- Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques
- Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition
- Investigation of the Contact Resistance between Ti/TiN and Ru in Metal-1/Plate Contacts of Ruthenium Insulator Silicon Capacitor
- Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance
- Innovative Al Damascene Process for Nanoscale Interconnects
- Highly Reliable 0.15 μm/14 F2 Cell Ferroelectric Random Access Memory Capacitor Using SrRuO3 Buffer Layer
- Most Efficient Alternative Manner of Patterning sub-80 nm Contact Holes and Trenches with 193 nm Lithography
- Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes