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Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci | 論文
- Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- Classification of Benign/Malignant PNGGOs using K-means algorithm in MDCT Images : A Preliminary Study(International Forum on Medical Imaging in Asia 2009 (IFMIA 2009))
- Analysis of random telegraph signal noise in dual and single oxide device and its application to complementary metal oxide semiconductor image sensor readout circuit (Special issue: Solid state devices and materials)
- Analysis of Random Telegraph Signal Noise in Dual and Single Oxide Device And Its Application to CMOS Image Sensor Readout Circuit
- FN stess induced degradation on random telegraph signal noise in deep submicron NMOSFETs (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- FN stess induced degradation on random telegraph signal noise in deep submicron NMOSFETs (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Accurate Extraction of the Trap Depth From RTS Noise Data By including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Accurate Extraction of the Trap Depth From RTS Noise Data By including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
- Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
- 4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- 4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
- Extended Word-Line NAND Flash Memory
- Silicon-Based Dual-Gate Single-Electron Transistors for Logic Applications
- Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor
- Extraction of Interface-States Energy Distribution in Nitrided and Pure Gate Dielectrics for Metal Oxide Semiconductor Field Effect Transistor Applications
- A New 1T DRAM Cell : Cone Type 1T DRAM Cell