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Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci | 論文
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
- Novel Gate-All-Around MOSFETs with Self-Aligned Structure
- Multi-Functionality of Novel Structured Tunneling Devices
- Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
- Nanoscale Poly-Si Line Formation and Its Uniformity (2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices(AWAD 2001))
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Design and Simulation of Asymmetric MOSFETs
- Integration Process of Impact-Ionization Metal-Oxide-Semiconductor Devices with Tunneling Field-Effect-Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors
- Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As_2^+ Å Low Energy Ion Implantations
- Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
- Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60nm MOSFETs
- Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))