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Cea-leti | 論文
- CMP-less Co-Integration of Tunable Ni-TOSI CMOS for Low Power Digital and Analog Applications
- Highly Manufacturable and Cost-effective Single Ta_xC / Hf_xZr_O_2 Gate CMOS Bulk Platform for LP Applications at the 45nm Node and Beyond
- Highly scalable and WF-tunable Ni(Pt)Si / SiON TOSI-gate CMOS devices obtained in a CMP-less integration scheme
- Effect of Process Induced Strain in 35nm FDSOI Devices with Ultra-Thin Silicon Channels
- Strained-Si for CMOS 65nm node : Si_Ge_ SRB or "Low Cost" approach?
- Scaling of Multiple-Gate Fully Depleted SOI Transistors
- 3D Stacked Nanowires CMOS Integration with a Damascene Finfet Process
- Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications
- Impact of Tunnel Etching Process on Electrical Performances of SON Devices
- Additivity between sSOI- and CESL-induced nMOSFETs Performance Boosts
- The Design and Fabrication of 0.35 μm Single-Polysilicon Self-Aligned Bipolar Transistors
- Precise Extraction of Metal Gate Work Function from Bevel Structures
- Control of Selectivity between SiGe and Si in Isotropic Etching Processes
- 直径10nmナノワイヤCMOSにおけるキャリア輸送に関する研究(IEDM特集(先端CMOSデバイス・プロセス技術))
- A High Pressure High Temperature Poly Buffer LOCOS (HP-HTPBL) Isolation Process for 1Gbit Density Non Volatile Memories
- High Performance Shallow Trench Isolation for High Density Flash Memory Cells
- A Post Gigabit Generation Flash Memory Shallow Trench Isolation Scheme. The LATI-STI Process (LArge Tilt Implanted Sloped Trench Isolation) Using 100% CMP Planarization
- Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels
- Blue Light-Emitting Diodes Grown on ZnO Substrates
- Blue Light-Emitting Diodes Grown on ZnO Substrates