3D Stacked Nanowires CMOS Integration with a Damascene Finfet Process

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概要

• 論文の詳細を見る
• 2007-09-19

著者

• BARNOLA S.

  CEA-LETI

• Hartmann J.

  Cea-leti

• Delaye V.

  Cea-leti

• Ghibaudo G.

  Imep Inpg-minatec

• ERNST T.

  CEA-LETI

• DUPRE C.

  CEA-LETI

• DORNEL E.

  CEA-LETI

• BARBE J.

  CEA-LETI

• BECU S.

  CEA-LETI

• VIZIOZ C.

  CEA-LETI

• ANDRIEU F.

  CEA-LETI

• HARTMANN J-M.

  CEA-LETI

• POIROUX T.

  CEA-LETI

• FAYNOT O.

  CEA-LETI

• GHIBAUDO G.

  IMEP, INPG-MINATEC

• DELEONIBUS S.

  CEA-LETI

• DELEONIBUS S.

  CEA/DRT-LETI

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• 3D Stacked Nanowires CMOS Integration with a Damascene Finfet Process
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