High Performance Shallow Trench Isolation for High Density Flash Memory Cells

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概要

• 論文の詳細を見る
• 1996-08-26

著者

• Guillaumot B.

  Stmicroelectronics

• DELEONIBUS S.

  CEA-LETI

• MARTIN F.

  CEA/DRT-LETI

• DELEONIBUS S.

  CEA/DRT-LETI

• DELEONIBUS S.

  LETI(CEA) Dept de Microelectronique

• MARTIN F.

  LETI(CEA) Dept de Microelectronique

• Heitzmann M.

  Leti(cea)

• GOBIL Y.

  LETI(CEA)

• DEMOLLIENS O.

  LETI(CEA)

• GUILLAUMOT B.

  SGS-THOMSON Department de Microelectronique

• CANDELIER P.

  LETI(CEA)

• GUIBERT J.

  LETI(CEA)

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• A High Pressure High Temperature Poly Buffer LOCOS (HP-HTPBL) Isolation Process for 1Gbit Density Non Volatile Memories
• High Performance Shallow Trench Isolation for High Density Flash Memory Cells
• A Post Gigabit Generation Flash Memory Shallow Trench Isolation Scheme. The LATI-STI Process (LArge Tilt Implanted Sloped Trench Isolation) Using 100% CMP Planarization

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