DELEONIBUS S. | CEA/DRT-LETI

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著作論文

3D Stacked Nanowires CMOS Integration with a Damascene Finfet Process
Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications
Additivity between sSOI- and CESL-induced nMOSFETs Performance Boosts
A High Pressure High Temperature Poly Buffer LOCOS (HP-HTPBL) Isolation Process for 1Gbit Density Non Volatile Memories
High Performance Shallow Trench Isolation for High Density Flash Memory Cells
A Post Gigabit Generation Flash Memory Shallow Trench Isolation Scheme. The LATI-STI Process (LArge Tilt Implanted Sloped Trench Isolation) Using 100% CMP Planarization

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