Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications
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概要
- 論文の詳細を見る
- 2004-09-15
著者
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Hartmann J.
Cea-leti
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Toffoli A.
Cea/drt-leti
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Guillaumot B.
Stmicroelectronics
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VIZIOZ C.
CEA-LETI
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POIROUX T.
CEA-LETI
-
DELEONIBUS S.
CEA-LETI
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VINET M.
CEA/DRT-LETI
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POIROUX T.
CEA/DRT-LETI
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WIDIEZ J.
STMicroelectronics
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LOLIVIER J.
CEA/DRT-LETI
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PREVITALI B.
CEA/DRT-LETI
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VIZIOZ C.
CEA/DRT-LETI
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BESSON P.
STMicroelectronics
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SIMON J.
CEA/DRT-LETI
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MARTIN F.
CEA/DRT-LETI
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MAITREJEAN S.
CEA/DRT-LETI
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HOLLIGER P.
CEA/DRT-LETI
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BIASSE B.
CEA/DRT-LETI
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CASSE M.
CEA/DRT-LETI
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ALLAIN F.
CEA/DRT-LETI
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LAFOND D.
CEA/DRT-LETI
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HARTMANN J.
CEA/DRT-LETI
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TRUCHE R.
CEA/DRT-LETI
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CARRON V.
CEA/DRT-LETI
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LAUGIER F.
CEA/DRT-LETI
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ROMAN A.
STMicroelectronics
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MORAND Y.
STMicroelectronics
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RENAUD D.
CEA/DRT-LETI
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MOUIS M.
IMEP (UMR CNRS/INPG/UJF)
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DELEONIBUS S.
CEA/DRT-LETI
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Casse M.
Cea-leti Minatec
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Allain F.
Cea-leti Minatec
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