Cho W‐j | Electronics Materials Kwangwoon University

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著作論文

Fabrication of Two-Layer stacked Poly-Si TFT CMOS Inverters Using Laser Crystallized channel with metal gate on Si Substrate
SOI-Based Nanoscale CMOS Device Technology(Session 6A Silicon Devices III,AWAD2006)
Analysis of Interface Property of SiGe-On-Insulator (SGOI) Substrate with a Strained-Si Layer for Nano-CMOS Device Applications(Session 4 Silicon Devices II,AWAD2006)
SOI-Based Nanoscale CMOS Device Technology(Session 6A Silicon Devices III,AWAD2006)
Analysis of Interface Property of SiGe-On-Insulator (SGOI) Substrate with a Strained-Si Layer for Nano-CMOS Device Applications(Session 4 Silicon Devices II,AWAD2006)
SOI-Based Nanoscale CMOS Device Technology
Analysis of Interface Property of SiGe-On-Insulator (SGOI) Substrate with a Strained-Si Layer for Nano-CMOS Device Applications
Analysis of Interface Property of SiGe-On-Insulator (SGOI) Substrate with a Strained-Si Layer for Nano-CMOS Device Applications
Ultrashallow Junction Formation Using Novel Plasma Doping Technology beyond 50nm MOS Devices
Ultra-Shallow Junction Formation using Novel Plasma Doping Technology beyond 50nm MOS Devices
Fabrication of 50nm Trigate Silicon On Insulator Metal-Oxide-Silicon Field-Effect Transistor without Source/Drain Activation Annealing
1.55 μm Gain in a Short Er^ -doped Zirconium Fluoride Glass Fiber

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