16-Qubit Quantum-Computing Emulation Based on High-Speed Hardware Architecture
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概要
- 論文の詳細を見る
A 16-qubit quantum-computing emulator executing quantum algorithms at high speed is proposed. By limiting the command of the quantum computing emulator to the minimum function required with the quantum algorithm, probability amplitudes are expressed with one bit and the functions of many qubits are integrated on a field programmable gate array (FPGA). As a result of implementing the emulator in the FPGA, it is found that the emulator has a 250 times higher-speed as compared with a software simulation by a general-purpose processor.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-04-15
著者
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Saito Kosuke
Department Of Frontier Informatics School Of Frontier Science University Of Tokyo
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Hoh Koichiro
Department Of Electronic Engineering Faculty Of Engineering The University Of Tokyo
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Fujishima Minoru
Department Of Electronic Engineering The University Of Tokyo
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Saito Kosuke
Department of Frontier Informatics, School of Frontier Sciences, Univerity of Tokyo, 5-1-5-703 Kashiwanoha, Kashiwa, Chiba 277-8561, Japan
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Hoh Koichiro
Department of Frontier Informatics, School of Frontier Sciences, Univerity of Tokyo, 5-1-5-703 Kashiwanoha, Kashiwa, Chiba 277-8561, Japan
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Fujishima Minoru
Department of Frontier Informatics, School of Frontier Sciences, Univerity of Tokyo, 5-1-5-703 Kashiwanoha, Kashiwa, Chiba 277-8561, Japan
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