16-Qubit Quantum-Computing Emulation Based on High-Speed Hardware Architecture

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概要

• 論文の詳細を見る
• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2003-04-30

著者

• Saito Kosuke

  Department Of Frontier Informatics School Of Frontier Science University Of Tokyo

• HOH Koichiro

  Department of Electronic Engineering, Faculty of Engineering, The University of Tokyo

• FUJISHIMA Minoru

  Department of Information and Communication Engineering, the University of Tokyo

• Fujishima Minoru

  Department Of Frontier Informatics School Of Frontier Science University Of Tokyo

関連論文

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• A Simple Model of a Single-Electron Floating Dot Memory for Circuit Simulation
• Estimation of Cotunneling in Single-Electron Logic and Its Suppression
• Cotunneling-Tolerant Single-Electron Logic
• 16-Qubit Quantum-Computing Emulation Based on High-Speed Hardware Architecture
• Accuracy Improvement of the Pipelined AD Converter by the Adjustment Using Its Chaotic Output
• Integrated Random-Signal Source Utilizing CMOS Chaos Multivibrator
• Physical Mechanism of Chaos in Thyristors and Coupled-Transistor Structures
• A Unified First Return Map Model for Various Types of Chaos Observed in the Thyristor
• 16-Qubit Quantum-Computing Emulation Based on High-Speed Hardware Architecture

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