Electronic Chaos in Silicon Thyristor

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概要

• 論文の詳細を見る
• 社団法人応用物理学会の論文
• 1994-01-30

著者

• Yasuda Yukio

  School Of Electrical Engineering And Electronics Toyohashi University Of Technology

• Yasuda Y

  Univ. Tokyo Tokyo Jpn

• HOH Koichiro

  Department of Electronic Engineering, Faculty of Engineering, The University of Tokyo

• YASUDA Yoh

  Division of Electrical and Computer Engineering, Faculty of Engineering, Yokohama National Universit

• Hoh Koichiro

  Department Of Electronic Engineering Faculty Of Engineering The University Of Tokyo

• Yasuda Yoh

  Division Of Electrical And Computer Engineering Yokohama National University

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• High-Performance Accumulated Back-Interface Dynamic Threshold SOI MOSFET (AB-DTMOS) with Large Body Effect at Low Supply Voltage
• Electronic Chaos in Silicon Thyristor
• The Origin of Dark Region in LPE GaP Associating with Macrostep Riser
• Characterization of SOS Films Grown with Amorphous Si Buffer Layers by MOS FET's
• Solute Redistribution in Laser Crystallization in Concentrated InAs-GaAs Alloy
• Epitaxial Growth of SOS Films with Amorphous Si Buffer Layer
• Estimation of Cotunneling in Single-Electron Logic and Its Suppression
• Cotunneling-Tolerant Single-Electron Logic
• 16-Qubit Quantum-Computing Emulation Based on High-Speed Hardware Architecture
• Accuracy Improvement of the Pipelined AD Converter by the Adjustment Using Its Chaotic Output
• Integrated Random-Signal Source Utilizing CMOS Chaos Multivibrator
• Initial Stage of Growth of Ge on (100)Si by Gas Source Molecular Beam Epitaxy Using GeH_4
• A Unified First Return Map Model for Various Types of Chaos Observed in the Thyristor
• 酸素ジェットによるシリコンの増速熱酸化〔英文〕 (電子材料技術の新展開)
• A Compactly Integrated Random-Signal Source Using Chaos Multivibrator
• Analysis of Chaos in Capacitance-npn-Transistor Pair and Its Application to Neuron Element
• Emulation of Quantum Computing by Parallel Finite Impulse Responses
• Estimation of Cotunneling in Single-Electron Logic and Its Suppression
• 16-Qubit Quantum-Computing Emulation Based on High-Speed Hardware Architecture

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