Estimation of Cotunneling in Single-Electron Logic and Its Suppression
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概要
- 論文の詳細を見る
- 1996-02-01
著者
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AMAKAWA Shuhei
Department of Semiconductor Electronics and Integration Science, Graduate school of advanced Science
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Amakawa S
School Of Engineering The University Of Tokyo
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HOH Koichiro
Department of Electronic Engineering, Faculty of Engineering, The University of Tokyo
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FUJISHIMA Minoru
Department of Information and Communication Engineering, the University of Tokyo
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FUKUI Hironobu
Department of Information and Communication Engineering, the University of Tokyo
関連論文
- RF CMOS Integrated Circuit: History, Current Status and Future Prospects
- Electronic Chaos in Silicon Thyristor
- Charging and Retention Times in Silicon-Floating-Dot-Single-Electron Memory
- A Simple Model of a Single-Electron Floating Dot Memory for Circuit Simulation
- Single-Electron Circuit Simulation (Special Issue on Technology Challenges for Single Electron Devices)
- Proposal of a Schottky-Barrier SET Aiming at a Future Integrated Device (Special Issue on New Concept Device and Novel Architecture LSIs)
- Correlated Electron-Hole Transport in Capacitively-Coupled One-Dimensional Tunnel Junction Arrays ( Quantum Dot Structures)
- Estimation of Cotunneling in Single-Electron Logic and Its Suppression
- Cotunneling-Tolerant Single-Electron Logic
- 16-Qubit Quantum-Computing Emulation Based on High-Speed Hardware Architecture
- Accuracy Improvement of the Pipelined AD Converter by the Adjustment Using Its Chaotic Output
- Integrated Random-Signal Source Utilizing CMOS Chaos Multivibrator
- Physical Mechanism of Chaos in Thyristors and Coupled-Transistor Structures
- A Unified First Return Map Model for Various Types of Chaos Observed in the Thyristor