Flattening Process of Si Surface below 1000°C Utilizing Ar/4.9%H2 Annealing and Its Effect on Ultrathin HfON Gate Insulator Formation
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To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon should be realized. In this paper, flattening process of Si surface below 1000°C utilizing Ar/4.9%H2 annealing and its effect on ultrathin HfON gate insulator formation were investigated. The Si(100) substrates were annealed using conventional rapid thermal annealing (RTA) system in Ar or Ar/4.9%H2 ambient for 1h. The surface roughness of Ar/4.9%H2-annealed Si was small compared to that of Ar-annealed Si because the surface oxidation was suppressed. The obtained root mean square (RMS) roughness was 0.08nm (as-cleaned: 0.20nm) in case of Ar/4.9%H2-annealed at 1000°C measured by tapping mode atomic force microscopy (AFM). The HfON surface was also able to be flattened by reduction of Si surface roughness. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. We obtained equivalent oxide thickness (EOT) of 0.79nm (as-cleaned: 1.04nm) and leakage current density of 3.5×10-3A/cm2 (as-cleaned: 6.1×10-1A/cm2) by reducing the Si surface roughness.
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- Flattening Process of Si Surface below 1000°C Utilizing Ar/4.9%H2 Annealing and Its Effect on Ultrathin HfON Gate Insulator Formation
- Fabrication process of pentacene-based vertical OFETs with HfO_2 gate insulator