Low-Damage Gate Etching With High Degree of Anisotropy in High-Density DRAM Cell
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概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 2002-04-30
著者
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Park J‐s
Hynix Semiconductor Inc. Cheongju Chungbuk Kor
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Park Joo-seog
Memory R&d Division Hynix Semiconductor Inc.
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Park J‐s
Memory R&d Division Hynix Semiconductor Inc.
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Kim N‐s
Department Of Semiconductor Engineering Chungbuk National University
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KIM Nam-Sung
Memory R&D Division, Hynix Semiconductor Inc.
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KIM Il-Gweon
Memory R&D Division, Hynix Semiconductor Inc.
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PARK Dae-Young
Memory R&D Division, Hynix Semiconductor Inc.
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Kim Il-gweon
Memory R&d Division Hynix Semiconductor Inc.
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Kim I‐g
Hynix Semiconductor Inc. Chungbuk Kor
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Kim Nam-sung
Memory R&d Division Hynix Semiconductor Inc.
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Park Dae-young
Memory R&d Division Hynix Semiconductor Inc.
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Kim N‐s
Systems On Silicon Manufacturing Co. Pte. Ltd. Singapore
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- Suppression of Anomalous Edge Channel Effect for 0.15μm DRAM Cell and Beyond
- Impact of Polymetal Gate Etch Post-Cleaning on Data Retention Time in Sub-micron DRAM Cells
- Low-Damage Gate Etching With High Degree of Anisotropy in High-Density DRAM Cell
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- Preparation and Characterization of RuO_x Thin Films by Liquid Delivery Metalorganic Chemical Vapor Deposition
- DRAM Reliability Degradation By Dynamic Operation Stress During Burn-In
- Impact of NF3-Added Interlayer Dielectric High Density Plasma Process on Hump Effect in Submicron n-type Metal Oxide Silicon Field Effect Transistor
- Impact of Ti Deposition and Subsequent RTA Process on Contact Resistivity Characteristics of W-Bit Line in Sub-Micron Dynamic Random Access Memory