DRAM Reliability Degradation By Dynamic Operation Stress During Burn-In

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概要

• 論文の詳細を見る
• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2003-04-30

著者

• Park Joo-seog

  Memory R&d Division Hynix Semiconductor Inc.

• KIM Nam-Sung

  Memory R&D Division, Hynix Semiconductor Inc.

• KIM Il-Gweon

  Memory R&D Division, Hynix Semiconductor Inc.

関連論文

• Suppression of Anomalous Edge Channel Effect for 0.15μm DRAM Cell and Beyond
• Impact of Polymetal Gate Etch Post-Cleaning on Data Retention Time in Sub-micron DRAM Cells
• Low-Damage Gate Etching With High Degree of Anisotropy in High-Density DRAM Cell
• DRAM Reliability Degradation By Dynamic Operation Stress During Burn-In
• Impact of NF_3-Added Interlayer Dielectric High Density Plasma Process on Hump Effect in Submicron n-type Metal Oxide Silicon Field Effect Transistor
• DRAM Reliability Degradation By Dynamic Operation Stress During Burn-In
• Impact of NF3-Added Interlayer Dielectric High Density Plasma Process on Hump Effect in Submicron n-type Metal Oxide Silicon Field Effect Transistor
• Impact of Ti Deposition and Subsequent RTA Process on Contact Resistivity Characteristics of W-Bit Line in Sub-Micron Dynamic Random Access Memory

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