Impacts of Self-Aligned Epitaxial Silicon Sliver(SESS)in Buried Channel-pFETs Elevated Source/Drain Using Dual-Spacer Structure

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Excellent short channel and junction characteristics in buried channel p-type field effect transistors(BC-pFETs)are obtained using the elevated source/drain(ESD)structure with a self-aligned shallow sliver of boron implanted epitaxial silicon. By employing a dual-spacer structure using high temperature oxide(HTO)and nitride, a self-aligned epitaxial silicon sliver(SESS)protruding laterally into the bottom edge of gate sidewall spacers is intentionally formed to reduce the series resistance of source/drain extension of BC-pFET while minimizing the faceting. The trade-off relation between SESS and face developments is revealed by the control of HTO thickness. As a result, the short channel characteristics of ESD employing SESS are improved without decreasing current drivability for sub-0.25 μm pFETs. Cumulative characteristics of p^+-n junction leakage and the contact resistance are also remarkably improved using the elevated junction structure.
社団法人応用物理学会の論文
2000-04-30