Reliability of Low Temperature Poly-Si GOLD (Gate-Overlapped LDD) Structure TFTs(Special Issue on Electronic Displays)
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概要
- 論文の詳細を見る
Low-temperature poly-Si thin film transistor with gate-overlapped LDD (GOLD) structure was fabricated. Reliability was evaluated using electrical stress method comparing conventional LDD and single drain structures. As previous researchers have reported, we have confirmed that the degradation of ON current and the field effect mobility was very small compared to conventional LDD or non-LDD structures. We have analyzed the reliability of the GOLD TFT using two-dimensional device simulator. We have clarified that vertical negative field plays a dominant role for improving the reliability in the GOLD TFT. Impact ionization occurs far from the interface between the oxide and poly-silicon by the vertical negative field. GOLD structure is promising for the realization of system on panel.
- 社団法人電子情報通信学会の論文
- 2002-11-01
著者
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Fuyuki Takashi
Department Of Electronic Science And Engineering Faculty Of Engineering Kyoto University
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Fuyuki T
Nara Inst. Sci. And Technol. Nara Jpn
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KAWAKITA Tetsuo
the Graduate School of Materials Science, Nara Institute of Science and Technology
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NAKAGAWA Hidehiro
the Graduate School of Materials Science, Nara Institute of Science and Technology
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URAOKA Yukiharu
the Graduate School of Materials Science, Nara Institute of Science and Technology
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FUYUKI Takashi
the Graduate School of Materials Science, Nara Institute of Science and Technology
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Uraoka Yukiharu
The Graduate School Of Materials Science Nara Institute Of Science And Technology
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Kawakita Tetsuo
The Graduate School Of Materials Science Nara Institute Of Science And Technology
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Nakagawa Hidehiro
The Graduate School Of Materials Science Nara Institute Of Science And Technology
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Fujii Tadashi
the Graduate School of Materials Science, Nara Institute of Science and Technology
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