Automatic Synthesis of a Serial Input Multiprocessor Array (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [ 1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial in-put processor array (PA). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.
- 社団法人電子情報通信学会の論文
- 1996-12-25
著者
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Kunieda Hiroaki
Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
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Kunieda Hiroaki
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
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LI Dongju
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
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Li Dongju
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
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Li Dongju
Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
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Li Dongju
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
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Kunieda Hiroaki
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
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