New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec
スポンサーリンク
概要
- 論文の詳細を見る
copyright(c)2002 IEICE許諾番号:08RB0009A new H.263+ rate control method that has very low encoder-decoder delay, small buffer and low computational complexity for hardware realization is proposed in this paper. This method focuses on producing low encoder-decoder delay in order to solve the lip synchronization problem. Low encoder-decoder delay is achieved by improving target bit rate achievement and reducing processing delay. The target bit rate achievement is improved by allocating an optimum frame encoding bits, and employing a new adaptive threshold of zero vector motion estimation. The processing delay is reduced by simplifying quantization parameter computation, applying a new non-zero coefficient distortion measure and utilizing previous frame information in current frame encoding. The simulation results indicate very large number skipped frames reduction in comparison with the test model TMN8. There were 80 skipped frames less than that of TMN8 within a 380 frame sequence during encoding of a very high movement video sequence. The 27 kbps target bit rate is achieved with insignificant difference for various types of video sequences. The simulation results also show that our method successfully allocates encoding bits, maintains small data at the encoder buffer and avoids buffer from overflow and underflow.
- 2002-06-01
著者
-
Kunieda H
Department Of Communication And Integrated System Tokyo Institute Of Technology
-
Ito Kazuhito
Department Of Electrical And Electronic Systems Engineering Saitama University
-
Ito Kazuhito
Department Of Applied Physics Grad. Sch. Of Engineering Nagoya University
-
Kunieda Hiroaki
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Kunieda H
Tokyo Inst. Of Technol. Tokyo Jpn
-
HONSAWEK Chawalit
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
-
Li Dongju
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Li D
Tokyo Inst. Technol. Tokyo Jpn
-
ISSHIKI Tsuyoshi
Department of Communications and Integrated Systems, Tokyo Institute of Technology
-
ADIONO Trio
Department of Communications and Integrated Systems, Tokyo Institute of Technology
-
Isshiki Tsuyoshi
Dept. Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Honsawek Chawalit
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Adiono Trio
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Li Dongju
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
-
Kunieda Hiroaki
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
-
Isshiki Tsuyoshi
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
-
伊藤 和人
Department of Communications and Integrated Systems, Tokyo Institute of Technology
関連論文
- 1P314 KaiCタンパク質の概日振動シミュレーションにおけるリン酸化サイクルとATPase活性の協調(非平衡・生体リズム,第48回日本生物物理学会年会)
- Entropy Decoding Processor for Modern Multimedia Applications
- New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec
- Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player
- A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development
- 2P-098 細胞分裂を考慮した分節時計の2次元シミュレーション(分子遺伝・遺伝情報制御,第47回日本生物物理学会年会)
- Design Optimization of VLSI Array Processor Architecture for Window Image Processing (Special Section on Digital Signal Processing)
- Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm(Special Section on Digital Signal Processing)
- Fast Fingerprint Classification Based on Direction Pattern(Image/Visual Signal Processing)(Digital Signal Processing)
- A Novel Fingerprint SoC with Bit Serial FPGA Engine (特集:システムLSIの設計技術と設計自動化)
- A New Approach for Datapath Synthesis of Application Specific Instruction Processor
- Automatic Synthesis of a Serial Input Multiprocessor Array (Special Section on VLSI Design and CAD Algorithms)
- Orientation Field Estimation for Embedded Fingerprint Authentication System
- Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC
- A Fingerprint Matching Using Minutia Ridge Shape for Low Cost Match-on-Card Systems(Digital Signal Processing)
- Binary Line-Pattern Algorithm for Embedded Fingerprint Authentication System(Image/Visual Signal Processing)(Digital Signal Processing)
- Systm-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications(Special Section on VLSI Design and CAD Algorithms)
- Unique Fingerprint-Image-Generation Algorithm for Line Sensors
- Bits Truncation Adaptive Pyramid Algorithm for Motion Estimation of MPEG2 (Special Section on Digital Signal Processing)
- Practical Orientation Field Estimation for Embedded Fingerprint Recognition Systems
- Narrow Fingerprint Sensor Verification with Template Updating Technique
- Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology
- A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing
- A Processor Accelerator for Software Decoding of Reed-Solomon Codes
- Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing
- A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine