Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC
スポンサーリンク
概要
- 論文の詳細を見る
A simple extension used to assist the decomposition of task-level concurrency within C programs is presented in this paper. The concurrency decomposition is meant to be used as the point of entry for Multiprocessor System-on-Chips (MPSoC) architectures design-flow. Our methodology allows the (re) use of readily available reference C programs and enables easy and rapid exploration for various alternatives of task partitioning strategies; a crucial task that greatly influences the overall quality of the designed MPSoC. A test case using a JPEG encoder application has been performed and the results are presented in this paper.
- (社)電子情報通信学会の論文
- 2008-07-01
著者
-
Kunieda H
Department Of Communication And Integrated System Tokyo Institute Of Technology
-
Kunieda Hiroaki
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Kunieda H
Tokyo Inst. Of Technol. Tokyo Jpn
-
Ullah Khan
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Li Dongju
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Li D
Tokyo Inst. Technol. Tokyo Jpn
-
ISSHIKI Tsuyoshi
Department of Communications and Integrated Systems, Tokyo Institute of Technology
-
ZALFANY URFIANTO
Department of Communications and Integrated Systems, Tokyo Institute of Technology
-
Zalfany Urfianto
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Isshiki Tsuyoshi
Dept. Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Li Dongju
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
-
Kunieda Hiroaki
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
-
Isshiki Tsuyoshi
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
関連論文
- Entropy Decoding Processor for Modern Multimedia Applications
- New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec
- Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player
- A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development
- Design Optimization of VLSI Array Processor Architecture for Window Image Processing (Special Section on Digital Signal Processing)
- Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm(Special Section on Digital Signal Processing)
- Fast Fingerprint Classification Based on Direction Pattern(Image/Visual Signal Processing)(Digital Signal Processing)
- A Novel Fingerprint SoC with Bit Serial FPGA Engine (特集:システムLSIの設計技術と設計自動化)
- A New Approach for Datapath Synthesis of Application Specific Instruction Processor
- Automatic Synthesis of a Serial Input Multiprocessor Array (Special Section on VLSI Design and CAD Algorithms)
- Orientation Field Estimation for Embedded Fingerprint Authentication System
- Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC
- A Fingerprint Matching Using Minutia Ridge Shape for Low Cost Match-on-Card Systems(Digital Signal Processing)
- Binary Line-Pattern Algorithm for Embedded Fingerprint Authentication System(Image/Visual Signal Processing)(Digital Signal Processing)
- Systm-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications(Special Section on VLSI Design and CAD Algorithms)
- Unique Fingerprint-Image-Generation Algorithm for Line Sensors
- Bits Truncation Adaptive Pyramid Algorithm for Motion Estimation of MPEG2 (Special Section on Digital Signal Processing)
- Practical Orientation Field Estimation for Embedded Fingerprint Recognition Systems
- Narrow Fingerprint Sensor Verification with Template Updating Technique
- Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology
- A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing
- Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing
- A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine