A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing
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概要
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Emerging image and video applications and conventional MPSoC architectures encounter drastically increasing performance and flexibility requirements. In order to display high quality images, large amount of image processing needs to be carried out. These image processing algorithms are nonstandard and vary case by case, and it is difficult to achieve real time processing by using general purpose processors or DSP. In this paper, we present two reconfigurable Application Specific Instruction-set Processors (ASIP) which can perform several image processing algorithms by using the same processor architecture. These ASIPs can achieve performance similar to DSP; meanwhile, while the area is considerably smaller than DSP and slightly bigger than conventional RISC processor. 1D ASIP can perform 16 times higher compared to a RISC processor, and 2D ASIP can perform 3 to 7 times higher compared to a RISC processor.
著者
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Li Dongju
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
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Kunieda Hiroaki
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
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Isshiki Tsuyoshi
Department Of Communication And Integrated System School Of Science And Engineering Tokyo Institute Of Technology
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Liao Hsuan-Chun
Department of Communications and Integrated Systems, Tokyo Institute of Technology
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Asri Mochamad
Department of Communications and Integrated Systems, Tokyo Institute of Technology
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