Reliability Evaluation of Thin Gate Oxide Using a Flat Capacitor Test Structure (Special Issue on Microelectronic Test Structure)
スポンサーリンク
概要
- 論文の詳細を見る
A test structure has been developed with very low-level current measurement technique and is used to evaluate a very small change of leakage current caused by the trapping and detrapping of electrons or holes. The present technique realizes detection of very low levels of leakage current (minimum detectable current is 5×10lt-17gt A), which is necessary in the course of evaluating gate oxides. This technique is very useful for the evaluation of retention characteristics and stress induced degradation of gate oxides.
- 社団法人電子情報通信学会の論文
- 1996-02-25
著者
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KOBAYASHI Kiyoteru
ULSI Laboratory, Mitsubishi Electric Corporation
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Mitsuhashi J
Ulsi Laboratory Evaluation Amp Analysis Center Mitsubishi Electric Corporation
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KATSUMATA Masafumi
ULSI Laboratory, Evaluation amp Analysis Center, Mitsubishi Electric Corporation
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MITSUHASHI Jun-ichi
ULSI Laboratory, Evaluation amp Analysis Center, Mitsubishi Electric Corporation
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MASHIKO Yoji
ULSI Laboratory, Evaluation amp Analysis Center, Mitsubishi Electric Corporation
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KOYAMA Hiroshi
ULSI Laboratory, Evaluation amp Analysis Center, Mitsubishi Electric Corporation
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Mashiko Y
Mitsubishi Electric Corp. Hyogo Jpn
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Mitsuhashi Jun-ichi
Ulsi Laboratory Mitsubishi Electric Corporation
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Mashiko Yoji
Ulsi Development Center Mitsubishi Electric Corp
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Kobayashi K
Kanagawa Industrial Technol. Res. Inst. Ebina‐shi Jpn
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Koyama Hiroshi
Ulsi Development Center Mitsubishi Electric Corporation:(present Address)jeol Limited
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Koyama Hiroshi
Ulsi Laboratory Evaluation Amp Analysis Center Mitsubishi Electric Corporation
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KOBAYASHI Kiyoteru
ULSI Laboratory, Evaluation amp Analysis Center, Mitsubishi Electric Corporation
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