B24-072 STRESS-OPTIMIZATION DESIGN OF A THIN-FILM SEMICONDUCTOR DEVICE
スポンサーリンク
概要
- 論文の詳細を見る
A stress-design technique for semiconductor devices was developed. This technique consists of a database-construction system, a stress-evaluation system, and a stress-simulation system. And it was used to improve the drain-current characteristic of a MOSFET. The stress simulation showed that the stress in the channel of the MOSFET was sensitive to the stress in a SIN film, which was deposited over the MOSFET. And the SiN film stress dependence of the drain current was experimentally clarified. In order to control the stress in the SiN film, germanium ions were implanted into the SiN film. As a result of this stress control, the drain current of an n-MOSFET increased by 13% without reducing that of a p-MOSFET.
- 一般社団法人日本機械学会の論文
- 2003-11-30
著者
-
SHIMIZU Akihiro
Hitachi ULSI Engineering Corp.
-
OHTA Hiroyuki
Mechanical Engineering Research Laboratory, Hitachi, Ltd.
-
Kumagai Yukihiro
Mechanical Engineering Research Laboratory Hitachi Lid.
-
Kumagai Yukihiro
Mechanical Engineering Research Laboratory Hitachi Ltd.
-
Ohta Hiroyuki
Mechanical Engineering Research Laboratory Hitachi Ltd.
-
MIURA HIDEO
Tohoku University
関連論文
- A 6.93-μm^2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
- A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers(Special Issue on the 1994 VLSI Circuits Symposium)
- Stress Analysis of Transistor Structures Considering the Internal Stress of Thin Films
- Stress Analysis in Silicon Substrates during Thermal Oxidation
- Residual Stress in Silicon Substrate with Shallow Trenches on Surface after Local Thermal Oxidation
- Residual Stress Measurement in Silicon Substrates after Thermal Oxidation
- Thermal Stability of Pt Bottom Electrodes for Ferroelectric Capacitors
- B24-072 STRESS-OPTIMIZATION DESIGN OF A THIN-FILM SEMICONDUCTOR DEVICE
- METHOD FOR PREDICTION OF DISLOCATION GENERATION IN SILICON SUBSTRATES OF SEMICONDUCTOR DEVICES
- Strain-Controlled Laterally Diffused Metal–Oxide–Semiconductor Transistor Utilizing Buried-Polysilicon Sinker as Stressor
- Stress Analysis for Chip–Package Interaction of Cu/Low-$k$ Multilayer Interconnects