A CMOS Charge-Pumping Circuit to Generate Substrate Bias Voltage
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概要
- 論文の詳細を見る
By controlling the substrate bias voltage of MOSFETs, the power reduction of VLSIs can be achieved while maintaing the switching speed of logic circuits. In this paper, we propose an efficent CMOS charge-pumping circuit to gernerate the substrate bias voltage. The output voltage of the circuit does not suffer voltage loss from the threshold voltage drop of pumping transistors. The operating characteristics of the circuit are also analyzed in detail. Further, the results obtained from these analysis are fully confirmed by experiments and simulations using the circuit analysis program H-SPICE.
- 東海大学の論文
著者
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YOSHIDA Masahiro
Department of Applied Chemistry and Chemical Engineering
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Saitoh Shin'ichi
Course Of Electrical Engineering Graduate School Of Engineering
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Teramoto Mitsuo
The Author Is With The Department Of Communications Eng. School Of Eng. Tokai University
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SUZUKI Yasoji
The author is with the Department of Communications Eng., School of Eng., Tokai University
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YOSHIDA Masahiro
The author is with the Department of Communications Eng., School of Eng., Tokai University
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SUZUKI Yasoji
Department of Comunications Engineering, School of Engineering
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TERAMOTO Mitsuo
Department of Comunications Engineering, School of Engineering
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Suzuki Yasoji
The Author Is With The Department Of Communications Eng. School Of Eng. Tokai University
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Suzuki Yasoji
Department Of Communication Engineering
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Yoshida Masahiro
The Author Is With The Department Of Communications Eng. School Of Eng. Tokai University
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Yoshida Masahiro
Department Of Applied Bioorganic Chemistry Gifu University
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