A High-Speed, Silicon-Based Few-Electron Memory Gain Cell
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概要
- 論文の詳細を見る
- 1999-09-20
著者
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Durrani Zahid
Microelectronics Research Centre Cavendish Laboratory University Of Cambridge:crest Jst (japan Scien
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Durrani Zahid
Microelectronics Research Centre University Of Cambridge Cavendish Laboratory
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Irvine Andrew
Microelectronics Research Centre University Of Cambridge Cavendish Laboratory
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Ahmed Haroon
Microelectronics Research Centre University Of Cambridge Cavendish Laboratory
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Ahmed Haroon
Microelectronics Research Center Cavendish Laboratory:crest Japan Science And Technology (jst)
関連論文
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- Transport Properties of Two Quantum Dots Connected in Series Formed in Silicon Inversion Layers
- Fabrication of Lateral Tunnel Junctions and Measurement of Coulomb Blockade Effects
- A High-Speed, Silicon-Based Few-Electron Memory Gain Cell
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- Performance of Silicon Based bi-directional Electron Pumps Consisting of Two Coulomb Blockade Devices
- Tunnel Barrier Formation in Silicon Nanowires
- Characteristics of Electron Pump Circuits Using Silicon Multiple Tunnel Junctions
- Single Atom Lithography and its Applications
- Characteristic of Electron Pumps Based on Silicon Coulomb Blockade Devices
- The Multiple-Tunnel Junction and Its Application to Single-Electron Memory and Logic Circuits
- Performance of Silicon Based Bi-Directional Electron Pumps Consisting of Two Coulomb Blockade Devices
- Modelling of Structural and Threshold Voltage Characteristics of Randomly Doped Silicon Nanowires in the Coulomb-Blockade Regime : Semiconductors