A Comprehensive Study of Punchthrough Characteristics in Multiple-Gate MOSFETs--The Trend of Punchthrough Voltages in Various Gate Shapes of SOI MOSFETs (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
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概要
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Punchthrough characteristics are investigated for different gate structures on silicon-on-insulator (SOI) FinFET. The punchthrough voltage (V_<PT>) was measured and verified by 3-D Silvaco simulator for various fin widths, crucial parameter to govern short-channel effects. The simulated results show a good agreement to the experimental data. Thereafter, the punchthrough voltages for multiple-gate structures in the SOI FinFETs: conventional FinFET, II-gate FinFET, Ω-gate FinFET and all-around-gate FinFET, were simulated with the aid of the Silvaco simulator after verification with experimental data. When the overlapped area of the gate-channel straddling the body increases, leakage paths reduce, and the punchthrough voltages increase as a result. For aggressive device scaling, all-around gate is highly preferable.
- 社団法人電子情報通信学会の論文
- 2005-06-21
著者
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Kang Hyun
Dept. Of Eecs Kaist
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Choi Yang
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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Choi Yang-kyu
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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Choi Yang
Dept. Of Eecs Kaist
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Ryu Seong
Dept. of EECS, Korea Advanced Institute of Science and Technology
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Ryu Seong
Dept. Of Eecs Kaist
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Ryu Seong-Wan
Dept. of EECS, KAIST
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Kang Hyun-Sik
Dept. of EECS, KAIST
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