Investigation of Gate Misalignment Effects in FinFETs(Session 7A Silicon Devices IV,AWAD2006)
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概要
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Gate misalignment effects on electrical properties of FinFETs have been investigated with three-dimensional (3-D) mixed-mode simulator. A major trade-off between S/D series resistances and diffusion capacitances was induced by the gate misalignment. The influences of series resistances on short channel effects of few tens nanometer device are discussed in detail. A SOI FinFET and a body-tied FinFET were compared in terms of FO4 inverter delay to assess the gate misalignment effects on circuit performance as a whole. In the SOI FinFET, source series resistance is dominant factor in determining RC delay, while drain diffusion capacitance is more significant in the body-tied FinFET.
- 社団法人電子情報通信学会の論文
- 2006-06-26
著者
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Han Jin-woo
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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Choi Yang-kyu
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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Kim Kuk-Hwan
Dept. of EECS, Korea Advanced Institute of Science and Technology
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Kim Kuk-hwan
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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Han Jin-Woo
Dept. of EECS, Korea Advanced Institute of Science and Technology
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Choi Yang-Kyu
Dept. of EECS, Korea Advanced Institute of Science and Technology
関連論文
- Investigation of Gate Misalignment Effects in FinFETs(Session 7A Silicon Devices IV,AWAD2006)
- Investigation of Gate Misalignment Effects in FinFETs(Session 7A Silicon Devices IV,AWAD2006)
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