Novel Structures for 2-Bit Per Cell of NVM Using Asymmetric Double Gate (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
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概要
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A 2-bit operational metal-oxide-nitride-oxide-silicon (MONOS) nonvolatile memory using an asymmetric double-gate (ASDG) MOSFET is studied to double the flash memory density. The 2-bit programming and erasing is performed by Fowler-Nordheim (FN) tunneling in a NAND array architecture using individually controlled gates. A threshold voltage shift of programmed states for the 2-bit operation was investigated with the aid of SILVACO^[○!R] simulator in the both sides of gate by changing gate workfunctions and tunneling oxide thicknesses. In this paper, guidelines of the 2-bit ASDG nonvolatile memory structure and operational conditions are proposed for "program", "read", and "erase".
- 社団法人電子情報通信学会の論文
- 2005-06-21
著者
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Choi Yang
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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Choi Yang-kyu
Electrical Eng. Dept. Nanobioelectronic Lab. Korean Advanced Inst. Of Science And Technology
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Choi Yang-kyu
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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Choi Yang
Dept. Of Eecs Kaist
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LEE Hyunjin
Dept. of EECS, Korea Advanced Institute of Science and Technology
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Kim Kuk
Dept. of EECS, Korea Advanced Institute of Science and Technology
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Kim Kuk
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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Kim Kuk-hwan
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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Lee Hyunjin
Dept. Of Eecs Korea Advanced Institute Of Science And Technology
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