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The Department Of Computer Science And Communication Engineering Graduate School Of Information Scie | 論文
- Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores(Special Section on VLSI Design and CAD Algorithms)
- RC-011 仮想キューによる高性能ハードウエアRTOSの実現(C分野:ハードウェア・アーキテクチャ,査読付き論文)
- Instruction Schecduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches (Special Section on VLSI Design and CAD Algorithms)
- Language and Compiler for Optimizing Datapath Widths of Embedded Systems (Special Section on VLSI Design and CAD Algorithms)
- Soft-Core Processor Architecture for Embedded System Design(Special Issue on Novel VLSI Processor Architectures)
- Memory Data Organization for Low-Energy Address Buses(Low-Power System LSI, IP and Related Technologies)
- Impacts of Compiler Optimizations on Address Bus Energy : An Empirical Study(VLSI Design Technology and CAD)
- A front-end for better behavioral synthesis
- A front-end for better behavioral synthesis
- Embedded System Cost Optimization via Data Path Width Adjustment (Special Issue on Synthesis and Verification of Hardware Design)
- Satsuki: An Integrated Processor Synthesis and Compiler Generation System (Special Issue on Synthesis and Verification of Hardware Design)
- Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
- Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
- Function Call Optimization for Efficient Behavioral Synthesis
- An RTOS-Based Design and Validation Methodology for Embedded Systems(System Programs)
- RTOS-Centric Cosimulator for Embedded System Design
- Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
- Systm-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications(Special Section on VLSI Design and CAD Algorithms)
- Module Selection Using Manufacturing Information (Special Section on VLSI Design and CAD Algorithms)
- RTOSのハードウェア化によるソフトウェアベースTCP/IP処理の高速化と低消費電力化(回路理論,回路解析)