Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores(Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• We present a new technique for hierarchical intellectual property(IP)protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.

• 社団法人電子情報通信学会の論文
• 2001-11-01

著者

• Date H

  First Laboratory Of The Institute Of Systems & Information Technologies Kyushu:(present Address)

• Chakrabarty Krishnendu

  The Department Of Electrical And Computer Engineering Duke University

• Iyengar Vikram

  The Department Of Electrical And Computer Engineering Duke University

• DATE Hiroshi

  First Laboratory of the Institute of Systems & Information Technologies Kyushu

• SUGIHARA Makoto

  the Department of Computer Science and Communication Engineering, Kyushu University

• Sugihara M

  Department Of Information And Computer Sciences Toyohashi University Of Technology

• Sugihara Makoto

  Toyohashi Univ. Technol. Toyohashi‐shi Jpn

• Sugihara Makoto

  The Department Of Computer Science And Communication Engineering Graduate School Of Information Scie

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