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Mitsubishi Electric Corp. Itami‐shi Jpn | 論文
- A Simple and Feasible Decision-Feedback Channel Tracking Scheme for MIMO-OFDM Systems(Advanced Transfer Technologies for the Next Generation Network)
- B-5-12 A New Fast Layered Ordering Method for MIMO Decision Feedback Equalization
- A Simplified Maximum Likelihood Detector for OFDM-SDM Systems in Wireless LAN(2004 International Symposium on Antennas and Propagation)
- B-5-196 A Novel QR-Decomposition-Aided Near Maximum Likelihood Detector in OFDM-SDM Systems(B-5. 無線通信システムB(ワイヤレスアクセス), 通信1)
- FPGA Implementation of Eigenbeam MIMO-OFDM for Wireless LAN and Its Experimental Performance(Software Defined Radio Technology and Its Applications)
- A 10-bit 50 MS/s 300 mW A/D Converter Using Reference Feed-Forward Architecture (Special Issue on Low-Power and High-Speed LSI Technologies)
- A Flexible Search Managing Circuitry for High-Density Dynamic CAMs (Speial Section on High Speed and High Density Multi Functional LSI Memories)
- A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories (Special Issue on LSI Memories)
- Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
- Mass Transport by a Vortex Ring : Classical Phenomenology and Applications
- Nonlocal Impact Ionization Model and Its Application to Substrate Current Simulation of n-MOSFET's
- Direct Efficiency and Power Calculation Method and Its Application to Low Voltage High Efflciency Power Amplifier
- Extraction of important sentences for speech summarization based on an F_0 model
- An Efficient Self-Timed Queue Architecture for ATM Switch LSIs (Special Issue on Multimedia, Analog and Processing LSIs)
- 111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method (Special Issue on ULSI Memory Technology)
- Alloyed and Non-Alloyed Ohmic Contacts for AlInAs/InGaAs High Electron Mobility Transistors
- Cooling Technology for MCFC Stack
- A 5.8 ns 256 kb SRAM with 0.4μm Super-CMOS Process Technology (Special Issue on Circuit Technologies for Memory and Analog LSIs)
- A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die (Special Issue on ULSI Memory Technology)
- Automatic Seal Imprint Verification System with Imprint Quality Assessment Function and Its Performance Evaluation