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Mitsubishi Electric Corp. Itami‐shi Jpn | 論文
- Intermodulation Distortion of Low Noise Silicon BJT and MOSFET Fabricated in BiCMOS Process (Special Issue on Low Distortion Technology for Microwave Devices and Circuits)
- A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology
- Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits (Special Issue on Low-power LSIs and Technologies)
- SOI/CMOS Circuit Design for High-Speed Communication LSIs (Special Issue on New Concept Device and Novel Architecture LSIs)
- An 80-MOPS-Peak High-Speed and Low-Power-Consumption 16-b Digital Signal Processor
- A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption
- 3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
- A New Emitter-Follower Circuit for High-Speed and Low-Power ECL
- Mechanism for Desorption of SiF_4 from an SiO_2 Film Surface in HF Solutions
- Mechanism for Desorption of SiF_4 from SiO_2 Film Surface in HF Solutions
- L-Band SPDT Switch Using Si-MOSFET (Special Issue on Microwave Devices for Mobile Communications)
- A Wideband Monolithic Lossy Match Power Amplifier Having an LPF/HPF-Combined Interstage Network
- Analysis of High Power Amplifier Instability due to f_0/2Loop Oscillation
- A Multi Phase-States MMIC Phase Shifter (Special Issue on Microwave Devices for Mobile Communications)
- Focused Ion Beam Trimming Techniques for MMIC Circuit Optimization (Special Issue on Microwave and Millimeter-Wave Technology for Advanced Functioions and Size-Reductions)
- Flip-Chip Mounted GaAs Power FET with Improved Performances in X to Ku Band : B-1: GaAs IC
- Fabrication and Characterization of Novel Oxide-Free InP Metal-Insulator-Semiconductor FETs Having an Ultra Narrow Si Surface Quantum Well
- Fabrication and Characterization of Novel Oxide-Free InP MISFETs Having an Ultra-Narrow Si Surface Quantum Well
- Improved Array Architectures of DINOR for 0.5 μm 32 M and 64 Mbit Flash Memories (Special Section on High Speed and High Density Multi Functional LSI Memories)
- Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))