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Microelectronics Engineering Laboratory, TOSHIBA Corp. | 論文
- Single Crystalline Silicon Floating Gate Technology for Sub-10nm Interelectrode Dielectrics
- Sub-1.3 nm Amorphous Tantalum Pentoxide Gate Dielectrics for Damascene Metal Gate Transistors
- Sub 1.3nm Amorphous Ta_2O_5 Gate Dielectrics for Damascene Metal Gate Transistor
- Highly Uniform Low-Pressure Chemical Vapor Deposition (LP-CVD) of Si_3N_4 Film on Tungsten for Advanced Low-Resistivity "Polymetal" Gate Interconnects
- Plasma-Damage-Free Gate Process Using Chemical Mechanical Polishing for 0.1 μm MOSFETs
- Plasma Damage Free Gate Process Using CMP for 0.1um MOSFETs
- Precipitation of Boron in Highly Boron-Doped Silicon
- New PentaCoordinated Si(PCS) Model for SiN CVD Mechanism
- Oxide-Mediated Solid Phase Epitaxy(OMSPE)of Silicon : A New Low-Temperature Epitaxy Technique Using Intentionally Grown Native Oxide
- Diffusion and Segregation of Carbon in SiO_2 Films
- Mechanism of Defect Formation during Low-Temperature Si Epitaxy on Clean Si Substrate
- Dominant Factor for the Concentration of Phosphorus Introduced by Vapor Phase Doping (VPD)
- Dominant Factor for the Concentration of Phosphorus Introduced by Vapor Phase Doping
- Influence of Reactive Ion Etching Applied to Si Substrate on Epitaxial Si Growth and Its Removal
- Highly Uniform Deposition of LP-CVD 3i3N4 Films on Tungsten for Advanced Low Resistivity "Poly-Metal" Gate Interconnects