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MIRAI-ASET | 論文
- ヘテロソース構造MOSFETにおけるチャネルへの高速電子注入(VLSI回路,デバイス技術(高速,低電圧,低電力))
- (110)面高性能ひずみSOI-CMOS素子技術(VLSI回路, デバイス技術(高速, 低電圧, 低電力))
- [特別招待論文]Sub-50-nm CMOSデバイス技術(VLSI回路, デバイス技術(高速, 低電圧, 低電力))
- [特別招待論文]Sub-50-nm CMOSデバイス技術(VLSI回路, デバイス技術(高速, 低電圧, 低電力))
- 微細CMOSスケーリングにおけるチャネル高移動度化の重要性 : Si/SiGe系ヘテロ構造による高移動度MOSFET
- Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process
- High Mobility Fully-Depleted Germanium-on-Insulator pMOSFET with 32-nm-Thick Ge Channel Layer Formed by Ge-Condensation Technique
- Performance Enhancement under High-Temperature Operation and Physical Origin of Mobility Characteristics in Ge-rich strained SiGe-on-Insulator pMOSFETs
- Evaluation of Dislocation Density of SiGe-on-Insulator Substrates using Enhanced Secco Etching Method
- Novel Fabrication Technique for Relaxed SiGe-on-Insulator Substrates without Thick SiGe Buffer Structures
- Strained-Si-on-Insulator (Strained-SOI) MOSFETs-Concept, Structures and Device Characteristics
- A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100nm Strained Silicon-on-Insulator MOSFETs
- A Novel Fabrication Technique of Ultra-Thin and Relaxed SiGe Buffer Layers with High Ge Content for Sub-100nm Strained Silicon-on-Insulator MOSFETs
- 溝側壁注入により逆狭チャネル効果を抑制した0.2μmSTI技術
- Siトンネリング選択成長によるせり上げSDE構造を持つSub-10-nm CMOSデバイス(先端CMOSデバイス・プロセス技術)
- Impact of Gradual Source/Drain Impurity Profiles on Performance of Germanium Channel Double-Gated pMISFETs
- High mobility Ge channel metal source/drain pMOSFETs with nickel fully silicided gate
- Ion-Implanted B Concentration Profiles in Ge
- Quantitative Evaluation of Interface Trap Density in Ge-MIS Interfaces
- Modulation of NiGe/Ge Schottky Barrier Height by Dopant and Sulfur Segregation during Ni Germanidation for Metal S/D Ge MOSFETs
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