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Kyoto Research Laboratory, Matsushita Electronics Corporation | 論文
- A DUV-Defined-Negative Resist/EB-Defined-positive Resist Two-Layer Resist System for the Fabrication of T-Shaped Gate : Lithography Technology
- A DUV-Defined-Negative Resist/EB-Defined-Positive Resist Two-Layer Resist System for the Fabrication of T-Shaped Gate
- Thermodynamics of Development Process of Positive Resists in Binary Mixed Developer
- Experimental and Theoretical Study of the Charge Build-Up in an ECR Etcher
- Observation Technique for Process-Induced Defects Using Anodic Oxidation (Special Issue on Scientific ULSI Manufacturing Technology)
- Epitaxial Lateral Overgrowth (ELO) of Silicon on the Whole Surface
- Stress-Induced Contact Failures in Al-Si/n-Si Structures
- Ferroelectric Nonvolatile Memory Technology and Its Applications
- Charge Build-Up and Uniformity Control in Magnetically Enhanced Reactive Ion Etching Using a Curved Lateral Magnetic Field
- Characteristics of a-Si Thin-Film Transistors with an Inorganic Black Matrix on the Top (Special Issue on Liquid-Crystal Displays)
- Back-Gate Effects of Amorphous-Si TFTs with an Inorganic Black Matrix on Array
- Particle Growth Caused by Film Deposition in VLSI Manufacturing Process (Special Issue on Scientific ULSI Manufacturing Technology)
- A Universal Relationship between Boron Penetration and Gate Oxide Reliability for Surface Channel PMOSFET
- High Reliability Trench Isolation Technology with Elevated Field Oxide Structure for Sub-Quarter Micron CMOS Devices
- Ferroelectric Nonvolatile Memory Technology and Its Applications