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Hitachi Ltd. Kokubunji‐shi Jpn | 論文
- A Hardware Implementation of a Neural Network Using the Parallel Propageted Targets Algorithm (Special Issue on Neurocomputing)
- A Hierarchical Classification Method for US Bank-Notes(Pattern Discrimination and Classification,Machine Vision Applications)
- A Neurocomputational Approach to the Correspondence Problem in Computer Vision (Special Issue on Neurocomputing)
- Derivation of New Equivalent Circuit for Interdigital Transducers with Leaky SAWs Using Integral Equation Approach
- Branch Micro-Architecture of an Embedded Processor with Split Branch Architecture for Digital Consumer Products(Special Issue on High-Performance and Low-Power Microprocessors)
- An Independent-Source Overdriven Sense Amplifier for Multi-Gigabit DRAM Array
- Multi-Input Feature Combination in the Cepstral Domain for Practical Speech Recognition Systems
- A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications(VLSI Architecture for Communication/Server Systems,VLSI Technology toward Frontiers of New Market)
- 100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet( The Next Generation Ethernet Technologies)
- A 35-GHz, 0.8-A/W and 26-μm Misalignment Tolerance Microlens-Integrated p-i-n Photodiodes
- Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router(Digital, Low-Power LSI and Low-Power IP)
- 動的セル形成セルラシステム実現に向けた伝搬路不整合の影響評価(移動通信ワークショップ)
- Effects of Rapid Thermal Annealing on Bias-Stress-Induced Base Leakage in InGaP/GaAs Collector-Up Heterojunction Bipolar Transistors Fabricated with B Ion Implantation(High-Speed HBTs and ICs,Heterostructure Microelectronics with TWHM2005
- A Hardware Accelerator for Java^ Platforms on a 130-nm Embedded Processor Core(Integrated Electronics)
- A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)
- Derivation of the Iteration Algorithm for the Modified Pseudo-Inverse Model for Associative Memory from the Consideration of the Energy Function
- A Comparison of Correlated Failures for Software Using Community Error Recovery and Software Breeding
- A Decentralized Clustering Scheme for Dynamic Downlink Base Station Cooperation
- Efficient Radix-2 Divider for Selecting Quotient Digit Embedded in Partial Remainder Calculation
- 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs