A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)

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概要

• 論文の詳細を見る

• A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-μm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5V and an ambient temperature of 75℃. The same margins 1.1 ns of the setup time and hold time were measured for the specifications of a setup time of 2.0 ns and a hold time of 0.5 ns.

• 社団法人電子情報通信学会の論文
• 1997-04-25

著者

• Toyoshima Hiroshi

  Hitachi VLSI Engineering Co., Ltd.

• Nishio Yoji

  Semiconductor Amp Integrated Circuits Division Hitachi Ltd.

• YAHATA Hideharu

  Semiconductor amp Integrated Circuits Division, Hitachi, Ltd.

• KOMIYAJI Kunihiro

  Semiconductor amp Integrated Circuits Division, Hitachi, Ltd.

• HIRAISHI Atsushi

  Semiconductor amp Integrated Circuits Division, Hitachi, Ltd.

• KINOSHITA Yoshitaka

  Semiconductor amp Integrated Circuits Division, Hitachi, Ltd.

• Hiraishi A

  Hitachi Ltd. Kokubunji‐shi Jpn

• Toyoshima H

  Hitachi Ulsi Engineering Corporation

• Komiyaji Kunihiro

  Semiconductor Amp Integrated Circuits Division Hitachi Ltd.

• Toyoshima Hiroshi

  Hitachi Vlsi Engineering Co. Ltd.

• Yahata Hideharu

  Semiconductor Amp Integrated Circuits Division Hitachi Ltd.

• Kinoshita Y

  Semiconductor Amp Integrated Circuits Division Hitachi Ltd.

• Kinoshita Yoshitaka

  Semiconductor Amp Integrated Circuits Division Hitachi Ltd.

• TOYOSHIMA Hiroshi

  Hitachi ULSI Engineering Corporation

関連論文

• A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers(Special Issue on the 1994 VLSI Circuits Symposium)
• A 10-b 50 MS/s 500-mW A/D Converter Using a Differential-Voltage Subconverter (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
• A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
• A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)

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