A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications(VLSI Architecture for Communication/Server Systems,<Special Section>VLSI Technology toward Frontiers of New Market)

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概要

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• A high-speed physical-layer architecture for next-generation higher-speed Ethernet for VSR and backplane applications was developed. VSR and backplane networks provide 100-Gb/s data transmission in "mega data centers" and blade servers, which have new and broad potential markets of LAN technologies. It supports 100-Gb/s-throughput, high-reliability, and low-latency data transmission, making it well suited to VSR and backplane applications for intra-building and intra-cabinet networks. Its links comprise ten 10-Gb/s high-speed serial lanes. Payload data are transmitted by ribbon fiber cables for very short reach and by copper channels for the backplane board. Ten lanes convey 320-bit data synchronously (32 bits×10 lanes) and parity data of forward-error correction code (newly developed (544, 512) code FEC), providing highly reliable (BER<1E-22) data transmission with a burst-error correction with low latency (31.0ns on the transmitter (Tx) side and 111.6ns on the receiver (Rx) side). A 64B/66B code-sequence-based skew compensation mechanism, which provides low-latency compensation for the lane-to-lane skew (less than 51ns), is used for parallel transmission. Testing this physical-layer architecture in an ASIC showed that it can provide 100-Gb/s data transmission with a 772-kgate circuit, which is small enough for implementation in a single LSI.

• 社団法人電子情報通信学会の論文
• 2007-10-01

著者

• OKUNO Michitaka

  Central Research Laboratory, Hitachi Ltd.

• Nishimura Shinji

  Central Research Laboratory Hitachi Ltd.

• Terada Matsuaki

  Faculty Of Engineering And Technology Tokyo University Of Agriculture And Technology

• Nishimura S

  Central Research Laboratory Hitachi Ltd.

• TOYODA Hidehiro

  Central Research Laboratory, Hitachi, Ltd.

• Okuno Michitaka

  Hitachi Ltd. Kokubunji‐shi Jpn

• Okuno Michitaka

  Central Research Laboratory Hitachi Ltd.

• Toyoda Hidehiro

  Central Research Laboratory Hitachi Ltd.

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• Cache-Based Network Processor Architecture : Evaluation with Real Network Traffic(Novel Device Architectures and System Integration Technologies)
• Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing( Development of Advanced Computer Systems)
• A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications(VLSI Architecture for Communication/Server Systems,VLSI Technology toward Frontiers of New Market)
• 100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet( The Next Generation Ethernet Technologies)
• Signal Transmission and Coding Architecture for Next-Generation Ethernet(New Technologies in the Internet and their Applications)
• Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router(Digital, Low-Power LSI and Low-Power IP)
• A Multi-Plane Packet Switch Based on Combined Packet Distribution and Hierarchical Priority Scheduling(Switching)

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