100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet(<Special Section> The Next Generation Ethernet Technologies)
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概要
- 論文の詳細を見る
A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 12×10-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits×10 lanes). One conveys forward error correction code ((132b, 140b) Hamming code), providing highly reliable (BER<10^<-12>) data transmission, and the other conveys parity data, enabling faultlane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the laneto-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590k gate circuit, which is small enough for implementation in a single LSI circuit.
- 社団法人電子情報通信学会の論文
- 2006-03-01
著者
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OKUNO Michitaka
Central Research Laboratory, Hitachi Ltd.
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Nishimura Shinji
Central Research Laboratory Hitachi Ltd.
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Nakahara Kouji
Central Research Laboratory Hitachi Ltd.
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Nishimura S
Central Research Laboratory Hitachi Ltd.
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Nishi Hiroaki
Keio Univ. Yokohama‐shi Jpn
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TOYODA Hidehiro
Central Research Laboratory, Hitachi, Ltd.
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FUKUDA Kouji
Central Research Laboratory, Hitachi, Ltd.
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NISHI Hiroaki
the Faculty of Science and Technology, Keio University
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Fukuda Kouji
Central Research Laboratory Hitachi Ltd.
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Okuno Michitaka
Hitachi Ltd. Kokubunji‐shi Jpn
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Okuno Michitaka
Central Research Laboratory Hitachi Ltd.
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Toyoda Hidehiro
Central Research Laboratory Hitachi Ltd.
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