Efficient Radix-2 Divider for Selecting Quotient Digit Embedded in Partial Remainder Calculation
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概要
- 論文の詳細を見る
This paper deals with an efficient radix-2 divider design theory that uses carry-propagation-free adders based on redundant binary {-1, 0, +1} representation. In order to compute the division fast, we look ahead to the next step quotient-digit selection embedded in the current partial remainder calculation. The solution is a function of the four most significant digits of the current partial remainder, when scaling the divisor in the range [1, 9/8). In gate depth, this result is better than the higher radix-4 case without the look-ahead quotient-digit selection and the design is simple.
- 社団法人電子情報通信学会の論文
- 1995-04-25
著者
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Tonomura M
Hitachi Ltd. Kokubunji‐shi Jpn
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Tonomura Motonobu
Hitachi Central Research Laboratory, Hitachi, Ltd.
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Tonomura Motonobu
Hitachi Central Research Laboratory Hitachi Ltd.
関連論文
- Efficient Radix-2 Divider for Selecting Quotient Digit Embedded in Partial Remainder Calculation
- Design Method for a Multimedia-Oriented Multiply-Adder (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Simple Quotient-Digit-Selection Radix4 Divider with Scaling Operation (Special Section on Discrete Mathematics and Its Applications)