Design Method for a Multimedia-Oriented Multiply-Adder (Special Issue on Low-Power High-Speed CMOS LSI Technologies)

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概要

• 論文の詳細を見る

• This paper describes a new design method for multiply-adders able to process a large quantity of multimedia data. I propose a (signed digits)×(unsigned digits) fixed-point multiply-add / subtract unit. The unit eliminates the problems caused by the critical one-bit arithmetic precision drop-off peculiar to the conventional (signed digits)×(signed digits) fixed-point multiply scheme. By simultaneously counting in the carry-save form, based on 7-3 counters simultaneously inputting the accumulation terms and the add / sub operation terms of multiplication results, carries are propagated faster than in the conventional method.

• 一般社団法人電子情報通信学会の論文
• 2000-02-25

著者

• Tonomura Motonobu

  Hitachi Central Research Laboratory Hitachi Ltd.

関連論文

• Efficient Radix-2 Divider for Selecting Quotient Digit Embedded in Partial Remainder Calculation
• Design Method for a Multimedia-Oriented Multiply-Adder (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
• Simple Quotient-Digit-Selection Radix4 Divider with Scaling Operation (Special Section on Discrete Mathematics and Its Applications)

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