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Advanced Lsi Technology Laboratory Research And Development Center Toshiba Corporation | 論文
- Advanced SOI MOSFET's with Strained-Si/SiGe Heterostructures(Joint Special Issue on Heterostructure Microelectronics with TWHM 2000)
- Novel Fabrication Technique for Relaxed SiGe-on-Insulator Substrates without Thick SiGe Buffer Structures
- A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100nm Strained Silicon-on-Insulator MOSFETs
- A Novel Fabrication Technique of Ultra-Thin and Relaxed SiGe Buffer Layers with High Ge Content for Sub-100nm Strained Silicon-on-Insulator MOSFETs
- Influence of High Dielectric Constant in Gate Insulator on Remote Coulomb Scattering due to Gate Impurities in Si MOS Inversion Layer
- Physical Origins of Surface Carrier Density Dependences of Interface- and Remote-Coulomb Scattering Mobility in Si MOS Inversion Layer
- Unified Roughness Scattering Model Incorporating Scattering Component Induced by Thickness Fluctuation in SOI MOSFETs
- Quantitative Understanding of Mobility Degradation in High Effective Electric Field Region in MOSFETs with Ultra-thin Gate Oxides
- Analytical Single-Electron Transistor(SET)Model for Design and Analysis of Realistic SET Circuits
- New Approach to Negative Differential Conductance with High Peak-to-Valley Ratio in Silicon
- Mobility Enhancement of SOI MOSFETs due to Subband Modulation in Ultrathin SOI Films
- Mobility Enhancement of SOI MOSFETs Due to Subband Modulation in Ultra-Thin SOI Films
- Observation of Oxide Thickness Dependent Interface Roughness in Si MOS Structure
- Non-Volatile Doubly Stacked Si Dot Memory with Si Nano-Crystalline Layer
- Novel Si Quantum Memory Structure with Self-Aligned Stacked Nanocrystalline Dots
- Influence of Channel Depletion on the Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory
- Experimental Analysis of Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory
- Double Junction Tunnel using Si Nanocrystalline Layer for Nonvolatile Memory Devices
- Unified Roughness Scattering Model Incorporating Scattering Component Induced by Thickness Fluctuations in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors (Special Issue: Solid State Devices & Materials)
- Power Consumption of Hybrid Circuits of Single-Electron Transistors and Complementary Metal-Oxide-Semiconductor Field-Effect Transistors