Park J‐h | Advanced Technology Development Team Memory Division Semiconductor Business Samsung Electronics Co.

スポンサーリンク

概要

関連著者

もっと見る

著作論文

Influence of Defect Segregation on the Electrical Properties of Nb-doped SrTiO_3 Grain Boundary Layer
Viewing Angle Enhancement of Three-Dimension/Two-Dimension Convertible Integral Imaging Display Using Double Collimated or Noncollimated Illumination
Numerical Analysis of One-Dimensional Magnetophotonic Crystals with an Active Layer of a Highly Bi-Substituted Iron Garnet
Degradation Phenomenon of p+to p+ Isolation Characteristics Caused by Carrier Injection in a High-Voltage Process
Process Design for Preventing the Gate Oxide Thinning in the Integration of Dual Gate Oxide Transistor
New STI Scheme to Compensate Gate Oxide Thinning at STI Corner Edge for the Devices Using Thick Dual Gate Oxide
Novel Capacitor Structure Using Sidewall Spacer for Highly Reliable Ferroelectric Random Access Memory Device
Robust Three-Metallization Back End of Line Process for 0.18μm Embedded Ferroelectric Random Access Memory
Influence of Grain boundary Layers on the Dielectric Relaxation of Nb-Doped SrTiO_3
Scaling of Three-Dimensional Integral Imaging
Depth-Enhanced Integral Imaging with a Stepped Lens Array or a Composite Lens Array for Three-Dimensional Display
The Hydrophilization of Process Wafers in Dilute Hydrogen Peroxide Solutions and Ozonated Deionized Water and Its Effects on Defects and Gate Oxide Integrity

もっと見る

スポンサーリンク