Reliability in Short-Channel p-Type Polycrystalline Silicon Thin-Film Transistor under High Gate and Drain Bias Stress

概要

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We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress ($\Delta V_{\text{TH}} = -2.08$ V), whereas that of long-channel TFTs was rarely shifted in the negative direction ($\Delta V_{\text{TH}} = -0.10$ V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance ($C_{\text{GD}}$) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage $V_{\text{FB}}$. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.
2010-03-25