High-Speed and Low-Power Source-Coupled Field-Effect Transistor-Logic-Type Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology
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概要
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We demonstrate a novel and compact implementation of high-speed and low-power source-coupled-field-effect transistor (FET)-logic (SCFL)-type non-return-to-zero (NRZ) delayed flip-flop circuit using resonant tunneling diode (RTD)/high electron mobility transistor (HEMT) integration technology on an InP substrate. The proposed circuit has several advantages of reduced device count, low power consumption, and reduced clock loading over previously reported circuits. The operations of the fabricated circuit was successfully confirmed up to 12.5 Gbits/s with a very low power consumption of about 11 mW.
- 2008-04-25
著者
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SEO Kwangseok
School of Electrical Engineering, Seoul National University
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Kim Hyungtae
School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Shillim-dong, Kwanak-gu, Seoul, 151-742, Korea
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Yeon Seongjin
School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea
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Seo Kwangseok
School of Electrical Engineer and Computer Science, Seoul National University, San 56-1, Shillim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea
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Yeon Seongjin
School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Shillim-dong, Kwanak-gu, Seoul, 151-742, Korea
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