Gate Length Reduction Technology for Pseudomorphic In0.52Al0.48As/In0.7Ga0.3As High Electron Mobility Transistors
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概要
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Gate length reduction technology was developed for pseudomorphic high-electron-mobility transistors (P-HEMTs) applicable to nano-HEMTs. This technology utilizes various reactions between plasmas and dielectrics. Using optimum conditions for reducing gate length through pattern transfer in dielectric etching, we fabricated HEMTs having a sub-30 nm gate length reduced from the initial gate length of 0.13 μm. A HEMT with this technology has merits of both fine length definition beyond the limit of an electron beam (e-beam) lithography system and overcoming the metal filling problem caused by a high aspect ratio. The fabricated devices have high DC and RF performance characteristics, a transconductance of 1.35 S/mm, a maximum saturated current of 800 mA/mm and a cutoff frequency $ f_{\text{T}}$ of 450 GHz.
- 2007-04-30
著者
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Yeon Seong-jin
School Of Electrical Engineering And Computer Science Seoul National University
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Seo Kwangseok
School of Electrical Engineer and Computer Science, Seoul National University, San 56-1, Shillim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea
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Seol Gyungseon
School of Electrical Engineer and Computer Science, Seoul National University, San 56-1, Shillim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea
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Seol Gyungseon
School of Electrical Engineering, Seoul National University, Shillim-dong, Kwanak-gu, Seoul 151-742, Korea
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Lee Jongwon
School of Electrical Engineering, Seoul National University, Shillim-dong, Kwanak-gu, Seoul 151-742, Korea
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Seo Kwangseok
School of Electrical Engineering, Seoul National University, Shillim-dong, Kwanak-gu, Seoul 151-742, Korea
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Yeon Seong-Jin
School of Electrical Engineering, Seoul National University, Shillim-dong, Kwanak-gu, Seoul 151-742, Korea
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