30 nm Triple-Gate In0.7GaAs HEMTs Fabricated by Damage-Free SiO2/SiNx Sidewall Process and BCB Planarization

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A 30 nm In0.7GaAs high electron mobility transistor (HEMT) with triple-gate has been successfully fabricated using the SiO2/SiNx sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten ($W$) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_{\text{g}}$), the etched-back BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low $R_{\text{g}}$ of 1.7 Ohm for a total gate width ($W_{\text{g}}$) of $2\times 100$ μm. The fabricated 30 nm In0.7GaAs HEMTs showed $V_{\text{th}}$ of $-0.4$ V, $G_{\text{m,max}}$ of 1.7 S/mm, and $f_{\text{T}}$ of 421 GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50 nm InGaAs HEMTs if the initial line length can be reduced to below 50 nm order.
2004-04-15