Low-Temperature Growth and Characterization of Epitaxial YMnO3/Y2O3/Si MFIS Capacitors with Thinner Insulator Layer

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YMnO3/Y2O3/Si capacitors were fabricated using an improved pulsed laser deposition (PLD) system with a dense YMnO3 target and a semiconductor laser heating system to solve the compositional distribution problem along the thickness of the YMnO3 films. As a result, the deposition temperature of the YMnO3 epitaxial films on Y2O3/Si could be lowered from 800 to 740°C. The epitaxial YMnO3/Y2O3/Si capacitors showed a ferroelectric capacitance–voltage ($C$–$V$) hysteresis loop with a memory window of 2.1 V, although the memory window did not saturate. To improve the electrical properties of the YMnO3/Y2O3/Si capacitors, the relationship between the thicknesses of the YMnO3 and Y2O3 layers and the applied voltage to each layer was calculated. The result indicates that a thickness less than 10 nm is required for the Y2O3 layer to bias the YMnO3 and Y2O3 layers equally. In this report, we discuss the fabrication of epitaxial YMnO3/Y2O3/Si capacitors with a 5-nm-thick Y2O3 layer using an improved PLD system. As a result of the optimization of the deposition conditions, epitaxial YMnO3(200 nm)/Y2O3(5 nm)/Si capacitors with a ferroelectric $C$–$V$ hysteresis loop was obtained.
2005-09-15